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Features
* * * * * * * * * * * * * *
Supply Voltage up to 40V RDSon Typically 0.8 at 25C, Maximum 1.5 at 150C Up to 1.0A Output Current Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers Capable of Switching Loads such as DC Motors, Bulbs, Resistors, Capacitors, and Inductors PWM Capability up to 25 kHz for Each High-side Output Controlled by External PWM Signal No Shoot-through Current Very Low Quiescent Current IS < 5 A in Standby Mode over Total Temperature Range Outputs Short-circuit Protected Selective Overtemperature Protection for Each Switch and Overtemperature Prewarning Undervoltage Protection Various Diagnostic Functions such as Shorted Output, Open Load, Overtemperature and Power-supply Fail Detection Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency QFN18 Package
Triple Half-bridge Driver with SPI and PWM ATA6831
1. Description
The ATA6831 provides fully protected driver interfaces designed in SOI technology. They are used to allow a microcontroller to control up to 3 different loads in automotive and industrial applications. Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to 1.0A. Due to the enhanced PWM signal (up to 25 kHz) it is possible to generate a smooth control of, for example, a DC motor without any noise. The drivers are internally connected to form 3 half-bridges and can be controlled separately from a standard serial data interface, enabling all kinds of loads, such as bulbs, resistors, capacitors and inductors, to be combined. The IC design especially supports the application of H-bridges to drive DC motors. Protection is guaranteed with respect to short-circuit conditions, overtemperature and undervoltage. Various diagnostic functions and a very low quiescent current in standby mode enable a wide range of applications. Automotive qualification (protection against conducted interferences, EMC protection and 2-kV ESD protection) gives added value and enhanced quality for exacting requirements of automotive applications.
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Figure 1-1.
Block Diagram
S I
O S C
O L D
P H 3
P L 3
P H 2
P L 2
P H 1
P L 1
H S 3
L S 3
H S 2
L S 2
H S 1
L S 1
S R R
10 VS1 11
Input register Ouput register
Serial interface
Charge pump L S 1 T P
VS2
DI 4
P S F
I N H
O V L
n. u.
n. u.
n. u.
n. u.
n. u.
n. H u. S 3
L S 3
H S 2
L S 2
H S 1
CLK 5
CS 3 DO 7 PWM 6 Control logic Power on reset 8 GND 14
Fault detector Fault detector Fault detector Fault detector Fault detector Fault detector
UV protection 9 VCC
GND Thermal protection 17 GND 18
1/2 OUT3
12/13 OUT2
15/16 OUT1
GND
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2. Pin Configuration
Figure 2-1. Pinning QFN18
PGND3 PGND1 OUT1S OUT1F PGND2 OUT2S
OUT3S OUT3F CS DI CLK PWM 1 2 3 4 5 6 18 17 16 15 14 13 12 11 10 9 8 7 OUT2F VS2 VS1 VCC GND DO
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Pin Description
Symbol OUT3S OUT3F CS DI CLK PWM DO GND VCC VS1 VS2 OUT2F OUT2S PGND2 OUT1F OUT1S PGND1 PGND3 Function Sense pin, used only for final testing Half-bridge output 3; formed by internally connecting power MOS high-side switch 3 and low-side switch 3 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load Chip select input; 5V CMOS logic level input with internal pull-up; low = serial communication is enabled, high = disabled Serial data input; 5V CMOS logic level input with internal pull-down; receives serial data from the control device; DI expects a 16-bit control word with LSB transferred first Serial clock input; 5V CMOS logic level input with internal pull-down; controls serial data input interface and internal shift register (fmax = 2 MHz) PWM input; 5V CMOS logic level input with internal pull-down Serial data output; 5V CMOS logic-level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB transferred first); output will remain tri-stated unless device is selected by CS = low; this allows several ICs to operate on only one data-output line Ground Logic supply voltage (5V) Power supply for output stages OUT1 and OUT2; internal supply Power supply for output stages OUT2 and OUT3; internal supply Half-bridge output 2; formed by internally connected power MOS high-side switch 2 and low-side switch 2 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load Sense pin, used only for final testing Power ground OUT2 Half-bridge output 1; formed by internally connected power MOS high-side switch 1 and low-side switch 1 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load Sense pin, used only for final testing Power ground OUT1 Power ground OUT3
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3. Functional Description
3.1 Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on the falling edge of the CLK signal. The LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1.
CS
Data Transfer
DI
SRR 0
LS1 1
HS1 2
LS2 3
HS2 4
LS3 5
HS3 6
nPL! 7
PH1 8
PL2 9
PH2 10
PL3 11
PH3 12
OLD 13
OCS 14 15
SI
CLK
DO
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OVl
INH
PSF
Table 3-1.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Input Data Protocol
Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 PL1 PH1 PL2 PH2 PL3 PH3 OLD OCS SI Function Status register reset (high = reset; the bits PSF and OVL in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 Output LS1 additionally controlled by PWM Input Output HS1 additionally controlled by PWM Input See PL1 See PH1 See PL1 See PH1 Open load detection (low = on) Overcurrent shutdown (high = overcurrent shutdown is active) Software inhibit; low = standby, high = normal operation (data transfer is not affected by the standby function because the digital part is still powered)
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Table 3-2.
Bit 0
Output Data Protocol
Output (Status) Register TP Function Temperature prewarning: high = warning Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR Description see LS1 Description see HS1 Description see LS1 Description see HS1 Not used Not used Not used Not used Not used Not used Over-load detected: set high, when at least one output is switched off by a short-circuit condition or an overtemperature event. Bits 1 to 6 can be used to detect the affected switch Inhibit: this bit is controlled by software (bit SI in input register) High = standby, low = normal operation Power-supply fail: undervoltage at pin VS detected
1
Status LS1
2
Status HS1
3 4 5 6 7 8 9 10 11 12 13
Status LS2 Status HS2 Status LS3 Status HS3 n. u. n. u. n. u. n. u. n. u. n. u. OVL
14 15
INH PSF
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After power-on reset, the input register has the following status:
Bit 15 SI H
Bit 14 OCS H
Bit 13 OLD H
Bit 12 PH3 L
Bit 11 PL3 L
Bit 10 PH2 L
Bit 9 PL2 L
Bit 8 PH1 L
Bit 7 PL1 L
Bit 6 HS3 L
Bit 5 LS3 L
Bit 4 HS2 L
Bit 3 LS2 L
Bit 2 HS1 L
Bit 1 LS1 L
Bit 0 SRR L
The following patterns are used to enable internal test modes of the IC. Do not use these patterns during normal operation.
Bit 15 Bit 14 H H H H H H
Bit 13 (OCS) H H H
Bit 12 H L L
Bit 11 H L L
Bit 10 L H L
Bit 9 L H L
Bit 8 L L H
Bit 7 L L H
Bit 6 (HS3) L L L
Bit 5 (LS3) L L L
Bit 4 (HS2) L L L
Bit 3 (LS2) L L L
Bit 2 Bit 1 (HS1) (LS1) L L L L L L
Bit 0 (SRR) L L L
3.2
Power-supply Fail
If undervoltage is detected at pin VS, the power-supply fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to last longer than the undervoltage detection delay time tdUV. The outputs are enabled immediately when the supply voltage returns to the normal operational value. The PSF bit stays high until it is reset by the SRR bit in the input register.
3.3
Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IOUT1-3). If the current through the external load does not reach the open-load detection current, the corresponding bit of the output in the output register is set to high. Switching on an output stage with the OLD bit set to low disables the open-load function for this output.
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3.4 Overtemperature Protection
If the junction temperature of one or more output stages exceeds the thermal prewarning threshold, T jPW set , the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word. The status of TP is available at pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the status of input and output registers. If the junction temperature of an output stage exceeds the thermal shutdown threshold, Tjswitch off, the affected output is disabled and the corresponding bit in the output register is set to low. Additionally, the overload detection bit (OVL) in the output register is set. The output can be enabled again when the temperature falls below the thermal shutdown threshold, Tjswitch on, and the SRR bit in the input register is set to high. The hysteresis of thermal prewarning and shutdown threshold avoids oscillations.
3.5
Short-circuit Protection
The output currents are limited by a current regulator. Overcurrent detection is activated by writing a high to the overcurrent shutdown bit (OCS) bit in the input register. When the current in an output stage exceeds the overcurrent limitation and shut-down threshold, it is switched off, following a delay time (tdSd). The over-load detection bit (OVL) is set and the corresponding status bit in the output register is set to low. For OCS = low, the overcurrent shutdown is inactive and the OVL bit is not set by an overcurrent. By writing a high to the SRR bit in the input register the OVL bit is reset and the disabled outputs are enabled.
3.6
Inhibit
The SI bit in the input register has to be set to zero to inhibit the ATA6831. In this state, all output stages are then turned off but the serial interface remains active. The current consumption is reduced to less than 5 A at pin VS and less than 100 A at pin VCC. The output stages can be reactivated by setting bit SI to "1".
3.7
PWM Mode
The common input for all six outputs is pin PWM (Figure 3-2). The selection of the outputs, which are controlled by PWM, is done by input data register PLx or PHx. In addition to the PWM input register, the corresponding input registers HSx and LSs have to be set. Switching the high side outputs is possible up to 25 kHz, low side switches up to 8 kHz. Figure 3-2. Output Control by PWM
Bit LSx/HSx Bit PLx/PHx Pin PWM Pin OUTx
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4. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Supply voltage t < 0.5s; IS > -2A Logic supply voltage Logic input voltage Logic output voltage Input current Output current Output current Output voltage Reverse conducting current (tpulse = 150 s) Junction temperature range Storage temperature range Pin 10, 11 10, 11 9 3, 4, 5, 6 7 3, 4, 5, 6 7 2, 12, 15 2, 12, 15 2, 12, 15 Symbol VVS VVS VVCC VCS, VDI, VCLK, VPWM VDO ICS, IDI, ICLK, IPWM IDO IOut1, IOut2, IOut3 IOut1, IOut2, IOut3 IOut1, IOut2, IOut3 TJ TSTG Value -0.3 to +40 -1 -0.3 to +7 -0.3 to VVCC + 0.3 -0.3 to VVCC + 0.3 -10 to +10 -10 to +10 Internally limited, see output specification -0.3 to +40 17 -40 to +150 -55 to +150 V A C C Unit V V V V V mA mA
5. Thermal Resistance
Parameters Thermal resistance from junction to case Thermal resistance from junction to ambient Depends on the PC board Test Conditions Symbol RthJC RthJA Value 15 40 Unit k/W K/W
6. Operating Range
Parameters Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency PWM input frequency Junction temperature range Note: 1. Threshold for undervoltage description Symbol VVS VVCC VCS, VDI, VCLK, VPWM fCLK fPWM Tj Value VUV(1) to 40 4.75 to 5.25 -0.3 to VVCC 2 max. 25 -40 to +150 Unit V V V MHz kHz C
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7. Noise and Surge Immunity
Parameters Conducted interferences Interference suppression ESD (Human Body Model) CDM (Charge Device Model) Note: 1. Test pulse 5: Vsmax = 40V Test Conditions ISO 7637-1 VDE 0879 Part 2 ESD S 5.1 ESD STM5.3.1 Value Level 4(1) Level 5 2 kV 500V
8. Electrical Characteristics
7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. 1 1.1 1.2 Parameters Current Consumption Quiescent current VS VVS < 20V, SI = low 10, 11 9 IVS IVCC 1 60 5 100 A A A A 4.75V < VVCC < 5.25V, Quiescent current VCC SI = low Supply current VS VVS < 20V normal operating, all outputs off, input register bit 13 (OLD) = high 4.75V < VVCC < 5.25V, normal operating VVS = 32.5V, INH = low VVS = 40V, INH = low Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1.3
10, 11
IVS
4
6
mA
A
1.4 1.5 1.6 2 2.1 2.2 2.3 2.4 2.5 3 3.1 3.2 3.3 3.4 3.5 Notes:
Supply current VCC Discharge current VS Discharge current VS Power-on reset threshold Power-on reset delay time
9 10, 11 10, 11
IVCC IVS IVS 0.5 2.5
350
650 5.5 10
A mA mA
A A A
Undervoltage Detection, Power-on Reset 9 After switching on VCC 10, 11 10, 11 VVCC tdPor VUv VUv tdUV 10 3.2 30 5.6 0.6 40 3.9 95 4.4 190 7.0 V s V V s A A A A A
Undervoltage-detection VCC = 5V threshold Undervoltage-detection VCC = 5V hysteresis Undervoltage-detection delay time Thermal Prewarning and Shutdown Thermal prewarning set Thermal prewarning reset Thermal prewarning hysteresis Thermal shutdown off Thermal shutdown on
TjPW set TjPW reset TjPW Tj switch off Tj switch on
120 105
145 130 15
170 155
C C K
B B B B B
150 135
175 160
200 185
C C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.
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8. Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. 3.6 3.7 Parameters Thermal shutdown hysteresis Ratio thermal shutdown off/thermal prewarning set Ratio thermal shutdown on/thermal prewarning reset Output Specification (OUT1 to OUT3) IOut 1-3 = -0.9 A On resistance 4.2 4.3 4.4 4.5 4.6 4.7 High-side output leakage current Low-side output leakage current High-side switch reverse diode forward voltage IOut 1-3 = -0.9 A VOut 1-3 H = 0V, output stages off VOut 1-3 L = VVS, output stages off IOut = 1.5A 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 RDSon1-3H RDSon1-3L IOut1-3H IOut1-3L VOut1-3 - VVS VOut1-3L IOut1-3 2 1.0 1.3 1.7 -15 300 2 1.5 1.5 A A V V A A A A A A A A Test Conditions
Pin
Symbol Tj switch off Tj switch off/ TjPW set Tj switch on/ TjPW reset
Min.
Typ. 15
Max.
Unit K
Type* B B
1.05
1.2
3.8 4 4.1
1.05
1.2
B
Low-side switch reverse IOut 1-3 L = -1.5A diode forward voltage High-side overcurrent limitation and shutdown 7.5V < VVS < 20V threshold Low-side overcurrent limitation and shutdown 7.5V < VVS < 20V threshold High-side overcurrent limitation and shutdown 20V < VVS < 40V threshold Low-side overcurrent limitation and shutdown 20V < VVS < 40V threshold Overcurrent shutdown delay time High-side open load detection current Low-side open load detection current Open load detection current ratio Input register bit 13 (OLD) = low, output off Input register bit 13 (OLD) = low, output off
4.8
IOut1-3
-1.7
-1.3
-1.0
A
A
4.9
IOut1-3
1.0
1.3
2.0
A
A
4.10 4.11 4.12 4.13 4.14
IOut1-3 tdSd
-2.0 10 -2.5 0.2 1.2
-1.3
-1.0 40 -0.2 2.5 3
A s mA mA
A A A A
2, 12, 15 2, 12, 15
IOut1-3H IOut1-3L IOLoutLX / IOLoutHX
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.
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8. Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. 4.15 4.16 4.17 4.18 Parameters Test Conditions
Pin
Symbol tdon tdon tdoff tdoff
Min.
Typ.
Max. 20 20 20 3
Unit s s s s
Type* A A A A
High-side output switch VVS = 13V RLoad = 30 on delay(1),(2) Low-side output switch VVS = 13V RLoad = 30 on delay(1),(2) High-side output switch VVS =13V off delay(1),(2) RLoad = 30 Low-side output switch VVS =13V RLoad = 30 off delay(1),(2) Dead time between corresponding high-side and low-side switches tdPWM low-side switch(3) tdPWM high-side switch(3) Input voltage low-level threshold Input voltage high-level threshold Hysteresis of input voltage Pull-down current pins DI, CLK, PWM Pull-up current pin CS VDI, VCLK, VPWM = VCC VCS = 0V VVS =13V RLoad = 30 VVS = 13V RLoad = 30 VVS = 13V RLoad = 30 3, 4, 5, 6 3, 4, 5, 6 3, 4, 5, 6 4, 5, 6 3
4.19
tdon - tdoff tdPWM = tdon - tdoff tdPWM = tdon - tdoff
1
s
A
4.20 4.21 5 5.1 5.2 5.3 5.4 5.5 6 6.1 6.2 6.3 7 7.1
20 3 7
s s
A A
Logic Inputs DI, CLK, CS, PWM VIL VIH VI IPD IPU 50 10 -65 0.3 x VVCC 0.7 x VVCC 700 65 -10 V V mV A A A A A A A
Serial Interface - Logic Output DO Output-voltage low level IDOL = 2 mA Output-voltage high level Leakage current (tri-state) Inhibit Input - Timing Delay time from standby to normal operation tdINH 100 s A IDOL = -2 mA VCS = VCC 0V < VDO < VVCC 7 7 7 VDOL VDOH IDO VVCC - 0.7V -10 10 0.4 V V A A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.
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9. Serial Interface Timing
No. 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 Parameters Test Conditions Pin Timing Chart No.(1) Symbol Min. Typ. Max. Unit Type* Serial Interface Timing DO enable after CS CDO = 100 pF falling edge DO disable after CS CDO = 100 pF rising edge DO fall time DO rise time DO valid time CS setup time CS setup time CS high time CLK high time CLK low time CLK period time CLK setup time CLK setup time DI setup time DI hold time CDO = 100 pF CDO = 100 pF CDO = 100 pF 7 7 7 7 7 3 3 3 5 5 5 5 5 4 4 1 2 10 4 8 9 5 6 7 3 11 12 tENDO tDISDO tDOf tDOr tDOVal tCSSethl tCSSetlh tCSh tCLKh tCLKl tCLKp tCLKSethl tCLKSetlh tDIset tDIHold 225 225 500 225 225 500 225 225 40 40 200 200 100 100 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns D D D D D D D D D D D D D D D
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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Figure 9-1. Serial Interface Timing with Chart Number
1 2
CS
DO
9
CS
4 7
CLK
5 3 6 8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC
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10. Application Circuit
Figure 10-1. Application Circuit
VCC
U5021M Watchdog
S I O S C O L D P H 3 P L 3 P H 2 P L 2 P H 1 P L 1 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 10 VS1 Input register Ouput register 11 Serial interface Charge pump L S 1 T P VS2
VS BYV28 VBatt 13V
Reset
Trigger
+
DI 4 CLK 5 CS 3
P S F
I N H
O V L
n. u.
n. u.
n. u.
n. u.
n. u.
n. H u. S 3
L S 3
H S 2
L S 2
H S 1
Microcontroller
Fault detector
Fault detector
Fault detector
UV protection 9 Control logic VCC Power on reset 8 GND
VCC VCC 5V
DO 7 PWM 6
+
Fault detector
Fault detector
Fault detector
14 GND Thermal protection 17 GND 18
VCC
2 OUT3
12 OUT2
15 OUT1
GND
M
M
10.1
Application Notes
* Connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. * Recommended value for capacitors at VS: - Electrolytic capacitor C > 22 F in parallel with a ceramic capacitor C = 100 nF. The value for the electrolytic capacitor depends on external loads, conducted interferences, and the reverse conducting current IOut1,2,3. * Recommended value for capacitors at VCC: - Electrolytic capacitor C > 10 F in parallel with a ceramic capacitor C = 100 nF. * To reduce thermal resistance, place cooling areas on the PCB as close as possible to the GND pins and to the die pad.
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11. Ordering Information
Extended Type Number ATA6831-PIQW ATA6831-PIPW ATA6831-PISW Package QFN18, 4 mm x 4 mm QFN18, 4 mm x 4 mm QFN18, 4 mm x 4 mm Remarks Taped and reeled, Pb-free Taped and reeled, Pb-free Tubes, Pb-free
12. Package Information
Package: VQFN_4 x 4_18L Exposed pad 2.5 x 3.125 Dimensions in mm Not indicated tolerances 0.05 Top 18 Pin 1 identification 3.1250.15 1 12 13 Z
Bottom 2.5 0.5 nom. 18 1 2.5 7 6 2.60.15
technical drawings according to DIN specifications
6
4
0.2 0.90.1
Z 10:1
Drawing-No.: 6.543-5133.01-4 Issue: preliminary copy; 06.10.06
0.230.07
0.450.1
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13. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History * * * * * * * * * * * * * * * * * * * * * * Features on page 1 changed Figure 1-1 "Block Diagram" on page 2 changed Section 2 "Pin Configuration" on pages 2 to 3 changed Section 4 "Absolute Maximum Ratings" on page 8 changed Section 8 "Electrical Characteristics" on pages 9 to 11 changed Section 9 "Serial Interface Timing" on page 12 changed Figure 10-1 "Application Circuit" on page 14 changed Section 11 "Ordering Information" on page 15 changed Section 12 "Package Information" on page 15 changed Title on page 1 changed Features on page 1 changed Figure 1-1 "Block Diagram" on page 1 changed Figure 2-1 "Pinning" on page 3 changed Table 2-1 "Pin Description" on page 3 changed Table 3-2 "Output Data Protocol" on page 5 changed Section 3.7 "PWM Mode" on page 7 added Section 4 "Absolute Maximum Ratings" on page 8 changed Section 8 "Electrical Characteristics" on pages 9 to 12 changed Figure 10-1 "Application Circuit" on page 14 changed Section 10.1 "Application Notes" on page 14 changed Section 11 "Ordering Information" on page 15 changed Section 12 "Package Information" on page 15 changed
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Atmel Corporation
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4908D-AUTO-09/06

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